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order this document by mc68hc812a4ec/d ? motorola inc, 1997, 1998 semiconductor motorola technical data preliminary 7/28/98 technical supplement mc68c812a4 3.3v electrical characteristics the mc68c812a4 is the low-voltage version of the standard mc68hc812a4 microcontroller unit (mcu), a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. modules include a 16-bit central processing unit (cpu12), a lite integration module (lim), two asynchronous serial communications interfaces (sci0 and sci1), a serial peripheral interface (spi), a timer and pulse accumulation module, an 8-bit analog-to-digital converter (atd), 1-kbyte ram, 4-kbyte eeprom, and memory expansion logic with chip selects, key wakeup ports, and a phase-locked loop (pll). this supplement contains the most accurate electrical information for the mc68c812a4 microcontroller available at the time of publication. the information should be considered preliminary and is subject to change. the following characteristics are contained in this document: table 1 maximum ratings table 2 thermal characteristics table 3 dc electrical characteristics table 4 supply current table 5 atd maximum ratings table 6 atd dc electrical characteristics table 7 analog converter characteristics (operating) table 8 atd ac characteristics (operating) table 9 eeprom characteristics table 10 control timing table 11 peripheral port timing table 12 non-multiplexed expansion bus timing table 13 spi timing
motorola mc68c812a4 2 preliminary notes: 1. permanent damage can occur if maximum ratings are exceeded. exposures to voltages or cur- rents in excess of recommended values affects device reliability. device modules may not operate normally while being exposed to electrical extremes. 2. refer to mc68hc812a4ts/d technical summary for complete part numbers. 3. one pin at a time, observing maximum power dissipation limits. internal circuitry protects the in- puts against damage caused by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any voltage higher than maximum-rated voltages to this high- impedance circuit. extended operation at the maximum ratings can adversely affect device reli- ability. tying unused inputs to an appropriate logic voltage level (either gnd or v dd ) enhances reliability of operation. notes: 1. this is an approximate value, neglecting p i/o . 2. for most applications p i/o ? p int and can be neglected. 3. k is a constant pertaining to the device. solve for k with a known t a and a measured p d (at equilibrium). use this value of k to solve for p d and t j iteratively for any value of t a . table 1 maximum ratings 1 rating symbol value unit supply voltage v dd , v dda , v ddx - 0.3 to + 6.5 v input voltage v in - 0.3 to + 6.5 v operating temperature range 2 mc68c812a4pv5 t a t l to t h 0 to + 70 c storage temperature range t stg - 55 to + 150 c current drain per pin 3 excluding v dd and v ss i in 25 ma v dd differential voltage v dd - v ddx 6.5 v table 2 thermal characteristics characteristic symbol value unit average junction temperature t j t a + (p d q ja ) c ambient temperature t a user-determined c package thermal resistance (junction-to-ambient) 112-pin thin quad flat pack (tqfp) q ja 39 c/w total power dissipation 1 p d p int + p i/o or w device internal power dissipation p int i dd v dd w i/o pin power dissipation 2 p i/o user-determined w a constant 3 k p d (t a + 273 c) + q ja p d 2 w c k t j 273 c + --------------------------
mc68c812a4 motorola 3 preliminary notes: 1. specification is for parts in the 0 to + 70 c range. higher temperature ranges will result in increased current leakage. table 3 dc electrical characteristics v dd = 3.3 vdc 0.3v, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol min max unit input high voltage, all inputs v ih 0.7 v dd v dd + 0.3 v input low voltage, all inputs v il v ss - 0.3 0.2 v dd v output high voltage all i/o and output pins normal drive strength i oh = - 10.0 m a i oh = - 0.8 ma reduced drive strength i oh = - 4.0 m a i oh = - 0.3 ma v oh v dd - 0.2 v dd - 0.8 v dd - 0.2 v dd - 0.8 v v v v output low voltage, all i/o and output pins, normal drive strength i ol = 10.0 m a i ol = 1.6 ma extal, pad[7:0], v rh , v rl , v fp , xirq , reduced drive strength i ol = 3.6 m a i ol = 0.6 ma v ol v ss + 0.2 v ss + 0.4 v ss + 0.2 v ss + 0.4 v v v v input leakage current 1 all inputs except irq , pad7, and xfc v in = v dd or v ss irq , pad7, xfc i in 1 10 m a m a three-state leakage, i/o ports, bkgd, and reset i oz 2.5 m a input capacitance all input pins and atd pins (non-sampling) atd pins (sampling) all i/o pins c in 10 15 20 pf pf pf output load capacitance all outputs except ps[7:4] ps[7:4] c l 90 130 pf pf active pull-up, pull-down current irq , xirq , eclk, lstrb , r/w , bkgd, moda, modb, arst ports a, b, c, d, f, g, h, j, s, t i apu 50 500 m a ram standby voltage, power down v sb 2.0 v ram standby current i sb 1ma
motorola mc68c812a4 4 preliminary note: i dd is tested with a rail-to-rail square wave on extal notes: 1. includes i dd and i dda . table 4 supply current v dd = 3.3 vdc 0.3v, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol 4 mhz 5 mhz unit maximum total supply current run: single-chip mode expanded mode i dd 15 21 17 25 ma ma wait: (all peripheral functions shut down) single-chip mode expanded mode w idd 3 3 3.5 3.5 ma ma stop: single-chip mode, no clocks s idd 250 250 m a maximum power dissipation 1 single-chip mode expanded mode p d 54 76 62 90 mw mw table 5 atd maximum ratings characteristic symbol value units atd reference voltage v rh v dda v rl 3 v ssa v rh v rl - 0.3 to + 6.5 - 0.3 to + 6.5 v v v ss differential voltage | v ss - v ssa | 0.1 v v dd differential voltage | v dd - v dda | v dd - v ddx 6.5 6.5 v v v ref differential voltage | v rh - v rl | 6.5 v reference to supply differential voltage | v rh - v dda | | v rl - v ssa | 6.5 6.5 v v
mc68c812a4 motorola 5 preliminary notes: 1. accuracy is guaranteed at v rh - v rl = 3.3 vdc 0.3v . 2. to obtain full-scale, full-range results, v ssa v rl v indc v rh v dda . 3. maximum leakage occurs at maximum operating temperature. current decreases by ap- proximately one-half for each 10 c decrease from maximum temperature. table 6 atd dc electrical characteristics v dd = 3.3 vdc 0.3v, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted characteristic symbol min max unit analog supply voltage v dda 3.0 3.6 v analog supply current normal operation i dda 1.0 ma reference voltage, low v rl v ssa v dda / 2v reference voltage, high v rh v dda / 2v dda v v ref differential reference voltage 1 v rh - v rl 3.0 3.6 v input voltage 2 v indc v ssa v dda v input current, off channel 3 i off 100 na reference supply current i ref 250 m a input capacitance not sampling sampling c inn c ins 10 15 pf pf
motorola mc68c812a4 6 preliminary notes: 1. v rh - v rl 3 3.072v 2. at v ref = 3.072v, one 8-bit count = 12 mv. 3. eight-bit absolute error of 2 counts (24 mv) includes 1/2 count (6 mv) inherent quantization error and 1 1/2 counts (18 mv) circuit (differential, integral, and offset) error. 4. maximum source impedance is application-dependent. error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. error from junction leakage is a function of external source impedance and input leakage current. expected error in result value due to junction leakage is expressed in voltage (v errj ): v errj = r s i off where i off is a function of operating temperature. charge-sharing effects with internal capacitors are a function of atd clock speed, the number of channels being scanned, and source impedance. for 8-bit conversions, charge pump leakage is computed as follows: v errj = .25pf v dda r s atdclk/(8 number of channels) table 7 analog converter characteristics (operating) v dd = 3.3 vdc 0.3v, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted characteristic symbol min typical max unit 8-bit resolution 1 2 counts 24 mv differential non-linearity 2 dnl - 0.5 + 0.5 count integral non-linearity 2 inl - 1 + 1 count absolute error 2,3 2, 4, 8, and 16 atd sample clocks ae - 2 + 2 count maximum source impedance r s 20 see note 4 k w table 8 atd ac characteristics (operating) v dd = 3.3 vdc 0.3v, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted characteristic symbol min max unit atd operating clock frequency f atdclk 0.5 2.0 mhz conversion time per channel 0.5 mhz f atdclk 2 mhz 18 atd clocks 32 atd clocks t conv 9.0 16.0 32.0 60.0 m s m s stop recovery time v dda = 3.3v t sr 50 m s
mc68c812a4 motorola 7 preliminary notes: 1. rc oscillator must be enabled if programming is desired and f sys < f prog . table 9 eeprom characteristics v dd = 3.3 vdc 0.3v, v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic symbol min typical max unit minimum programming clock frequency 1 f prog 3.0 mhz programming time t prog 20 ms clock recovery time following stop, to continue programming t crstop t prog + 1ms erase time t erase 20 ms write/erase endurance 10,000 30,000 cycles data retention 10 years table 10 control timing characteristic symbol 5.0 mhz unit min max frequency of operation f o dc 5.0 mhz e-clock period t cyc 200 ns crystal frequency f xtal 10.0 mhz external oscillator frequency 2f o dc 10.0 mhz processor control setup time t pcsu = t cyc / 2 + 30 t pcsu 130 ns reset input pulse width to guarantee external reset vector minimum input time (can be preempted by internal reset) pw rstl 32 2 t cyc t cyc mode programming setup time t mps 4t cyc mode programming hold time t mph 10 ns interrupt pulse width, irq , edge-sensitive mode, kwu pw irq = 2t cyc + 20 pw irq 420 ns wait recovery startup time t wrs 4t cyc timer pulse width, input capture pulse accumulator input pw tim = 2t cyc + 20 pw tim 420 ns
motorola mc68c812a4 8 preliminary figure 1 timer inputs pt7 2 pt7 1 pt[7:0] 2 pt[7:0] 1 timer input timing notes : 1. rising edge sensitive input 2. falling edge sensitive input pw tim pw pa
mc68c812a4 motorola 9 preliminary figure 2 por and external reset timing diagram t pcsu internal moda, modb eclk extal v dd reset 4098 t cyc free fffe fffe 3rd 1st 2nd free fffe fffe fffe t mph pw rstl t mps por ext reset tim address pipe pipe pipe 1st exec 3rd pipe 2nd pipe 1st pipe 1st exec note: reset timing is subject to change.
motorola mc68c812a4 10 preliminary figure 3 stop recovery timing diagram pw irq t stopdelay 3 irq 1 irq or xirq eclk 1st address 4 sp-9 free free vector free free resume program with instruction which follows the stop instruction. internal address 5 stop recovery tim clocks notes: 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) 3. t stopdelay = 4098 t cyc if dly bit = 1 or 2 t cyc if dly = 0. 4. xirq with x bit in ccr = 1. 5. irq or (xirq with x bit in ccr = 0). opt 1st 2nd 3rd 1st exec pipe pipe exec sp-8 sp-6 fetch pipe sp-6 sp-8 sp-9
mc68c812a4 motorola 11 preliminary figure 4 wait recovery timing diagram wait recovery tim t pcsu pc, iy, ix, b:a, , ccr stack registers eclk r/w address irq , xirq , or internal interrupts sp C 2 sp C 4 sp C 6 . . . sp C 9 sp C 9 sp C 9 . . . sp C 9 sp C 9 vector free 1st 2nd 3rd pipe t wrs note: reset also causes recovery from wait. address pipe pipe 1st exec
motorola mc68c812a4 12 preliminary figure 5 interrupt timing diagram interrupt tim eclk pw irq 1st 3rd address irq 1 sp C 9 t pcsu irq 2 , xirq , or internal interrupt vector sp C 2 1st sp C 4 sp C 6 2nd sp C 8 data vect pc iy ix b:a ccr prog r/w notes: 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) fetch addr exec pipe pipe pipe prog fetch prog fetch
mc68c812a4 motorola 13 preliminary figure 6 port read timing diagram figure 7 port write timing diagram table 11 peripheral port timing characteristic symbol 5.0 mhz unit min max frequency of operation (e-clock frequency) f o dc 5.0 mhz e-clock period t cyc 200 ns peripheral data setup time mcu read of ports t pdsu = t cyc / 2 + 30 t pdsu 130 ns peripheral data hold time mcu read of ports t pdh 0ns delay time, peripheral data write mcu write to ports t pwd 40ns port rd tim eclk mcu read of port ports t pdsu t pdh port wr tim eclk mcu write to port previous port data new data valid port a t pwd
motorola mc68c812a4 14 preliminary notes: 1. all timings are calculated for normal port drives. 2. this characteristic is affected by clock stretch. add n t cyc where n = 0, 1, 2, or 3, depending on the number of clock stretches. table 12 non-multiplexed expansion bus timing v dd = 3.3 vdc 0.3v, v ss = 0 vdc, t a = t l to t h , unless otherwise noted num characteristic 1 delay symbol 5 mhz unit min max frequency of operation (e-clock frequency) f o dc 5.0 mhz 1 cycle time t cyc = 1 / f o t cyc 200 ns 2 pulse width, e low pw el = t cyc / 2 + delay - 2pw el 98 ns 3 pulse width, e high 2 pw eh = t cyc / 2 + delay - 2pw eh 98 ns 5 address delay time t ad = t cyc / 4 + delay 29 t ad 79ns 6 address hold time t ah 20 ns 7 address valid time to e rise t av = pw el - t ad t av 28 ns 11 read data setup time t dsr 30 ns 12 read data hold time t dhr 0ns 13 write data delay time t ddw = t cyc / 4 + delay 25 t ddw 75ns 14 write data hold time t dhw 20 ns 15 write data setup time 2 t dsw = pw eh - t ddw t dsw 23 ns 16 read/write delay time t rwd = t cyc / 4 + delay 20 t rwd 70ns 17 read/write valid time to e rise t rwv = pw el - t rwd t rwv 28 ns 18 read/write hold time t rwh 20 ns 19 low strobe delay time t lsd = t cyc / 4 + delay 20 t lsd 70ns 20 low strobe valid time to e rise t lsv = pw el - t lsd t lsv 28 ns 21 low strobe hold time t lsh 20 ns 22 address access time 2 t acca = t cyc - t ad - t dsr t acca 100 ns 23 access time from e rise 2 t acce = pw eh - t dsr t acce 68ns 26 chip select delay time t csd = t cyc / 4 + delay 29 t csd 79ns 27 chip select access time 2 t accs = t cyc - t csd - t dsr t accs 100 ns 28 chip select hold time t csh 010ns 29 chip select negated time t csn = t cyc / 4 + delay 5 t csn 55 ns
mc68c812a4 motorola 15 preliminary figure 8 non-multiplexed expansion bus timing diagram eclk r/w 1 6 data[15:0] data[15:0] 2 3 18 22 11 12 13 14 addr[15:0] note: measurement points shown are 20% and 70% of v dd 5 15 bus tim cs 16 27 28 17 read write 23 lstrb 21 19 20 (w/o tag enabled) 26 29 7
motorola mc68c812a4 16 preliminary notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. table 13 spi timing v dd = 3.3 vdc 0.3v , v ss = 0 vdc, t a = t l to t h , 130 pf load on all spi pins 1 num function symbol min max unit operating frequency master slave f op dc dc 1 / 2 1 / 2 e-clock frequency 1 sck period master slave t sck 2 2 256 t cyc t cyc 2 enable lead time master slave t lead 1 / 2 1 t sck t cyc 3 enable lag time master slave t lag 1 / 2 1 t sck t cyc 4 clock (sck) high or low time master slave t wsck t cyc - 60 t cyc - 30 128 t cyc ns ns 5 sequential transfer delay master slave t td 1 / 2 1 t sck t cyc 6 data setup time (inputs) master slave t su 30 30 ns ns 7 data hold time (inputs) master slave t hi 0 30 ns ns 8 slave access time t a 1t cyc 9 slave miso disable time t dis 1t cyc 10 data valid (after sck edge) master slave t v 50 50 ns ns 11 data hold time (outputs) master slave t ho 0 0 ns ns 12 rise time input output t ri t ro t cyc - 30 30 ns ns 13 fall time input output t fi t fo t cyc - 30 30 ns ns
mc68c812a4 motorola 17 preliminary a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) figure 9 spi timing diagram (1 of 2) spi master cpha0 sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 10 6 7 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 5 3 12 13 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. spi master cpha1 sck (output) sck (output) miso (input) mosi (output) 1 6 7 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 10 12 13 11 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 5 2 13 12 3 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb.
motorola mc68c812a4 18 preliminary a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) figure 10 spi timing diagram (2 of 2) spi slave cpha0 sck (input) sck (input) mosi (input) miso (output) ss (input) 1 10 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 11 4 4 2 8 (cpol = 0) (cpol = 1) 5 3 13 note: not defined but normally msb of character just received. slave 13 12 11 see 12 note 9 spi slave cpha1 sck (input) sck (input) mosi (input) miso (output) 1 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 10 12 13 11 see (cpol = 0) (cpol = 1) ss (input) 5 2 13 12 3 note: not defined but normally lsb of character just received. slave note 8 9

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